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? e90602g0x-ps sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. absolute maximum ratings (ta=25 ?) supply voltage av dd , dv dd 7v input voltage (all pins) v in v dd +0.5 to v ss ?.5 v output current (every each channel) i out 0 to 15 ma storage temperature tstg ?5 to +150 ? recommended operating conditions supply voltage av dd , av ss 4.75 to 5.25 v dv dd , dv ss 4.75 to 5.25 v reference input voltage v ref 2.0 v clock pulse width t pw1 , t pw0 11.2 ns (min.) to 1.1 s (max.) operating temperature topr ?0 to +85 ? description the CXD1177Q is an 8-bit high-speed d/a converter for video band use. it has an input/output equivalent to 2 channels of y and c. it is suitable for use of digital tv, graphic display, and others. features resolution 8-bit maximum conversion speed 40msps yc 2-channel input/output differential linearity error 0.3 lsb low power consumption 160 mw (200 ? load at 2 vp-p output) single 5 v power supply low glitch noise stand-by function structure silicon gate cmos ic 8-bit 40msps yc 2-channel d/a converter 32 pin qfp (plastic) CXD1177Q
? CXD1177Q block diagram pin configuration 2lsb's current cells 6msb's current cells clock generator latches decoder 31 32 19 20 21 23 24 25 26 27 28 29 30 2lsb's current cells 6msb's current cells clock generator latches decoder 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 current cells (for full scale) bias voltage generator decoder decoder 22 dv dd av dd yo yo yck av ss dv ss co co cck vg vref iref vb (lsb) y0 y1 y2 y3 y4 y5 y6 (msb) y7 (lsb) c0 c1 c2 c3 c4 c5 c6 (msb) c7 blk ce 17 18 19 20 21 22 23 24 9 10 11 12 13 14 15 16 2 3 4 5 6 7 8 1 26 27 28 29 30 31 32 25 c7 c6 c5 c4 c3 c2 c1 c0 vref co co yo yo vg av dd dv dd iref avss vb dvss cck yck ce blk y0 y1 y2 y3 y4 y5 y6 y7
3 CXD1177Q pin description and i/o pins equivalent circuit 1 to 8 9 to 16 17 22 19 20 21 23 18 y0 to y7 c0 to c7 blk vb yck cck dv ss av ss ce i i o i i pin no. symbol i/o equivalent circuit description 1 dv dd dv ss to 16 dv dd dv ss 17 dv dd dv ss dv dd 22 dv dd dv ss 19 20 dv dd dv ss 18 digital input y0 (lsb) to y7 (msb) c0 (lsb) to c7(msb) blanking input. this is synchronized with the clock input signal for each channel. no signal at h (output 0 v). output condition at l . connect a capacitor of about 0.1 f. clock input. note) even though only 1 channel is used, be sure to input the clock signal to yck. digital ground analog ground chip enable input. this is not synchronized with the clock input signal. no signal (output 0 v) at h and minimizes power consumption.
4 CXD1177Q 24 25 30 31 27 29 26 28 32 iref vref vg av dd co yo co yo dv dd o i o o pin no. symbol i/o equivalent circuit description av ss av ss av dd av dd av ss av dd 24 25 30 av dd av dd av ss av dd av ss 26 27 28 29 connect a resistance 16 times r ir that of output resistance value r out . set full-scale output value. connect a capacitor of about 0.1 f. analog power supply current output. voltage output can be obtained by connecting a resistance. inverted current output. normally dropped to analog ground. digital power supply
5 CXD1177Q electrical characteristics (f clk =40 mhz, av dd =dv dd =5 v, r out =200 ? , v ref =2.0 v, ta=25 c) full-scale voltage for each channel ? 1 full-scale output ratio = full-scale voltage average value for each channels 1 100 (%) ? 2 when the external capacitors for the vg pins are 0.1 f. electrical characteristics measurement circuit analog input resistance measurement circuit digital input current CXD1177Q +5.25v av dd , dv dd av ss , dv ss v a } item resolution conversion speed integral non-linearity error differential non-linearity error output full-scale voltage output full-scale ratio ? 1 output full-scale current output offset voltage glitch energy crosstalk supply current analog input resistance input capacitance digital input voltage digital input current setup time hold time propagation delay time ce enable time ? 2 ce disable time ? 2 symbol n f clk e l e d v fs f sr i fs v os ge ct i dd i stb r in c i v ih v il i ih i il ts th t pd t e t d measurement conditions av dd =dv dd =4.75 to 5.25 v ta= 40 to +85 c endpoint when 00000000 data input r out =75 ? when 1 khz sine wave input when 14.3 mhz ce=l color bar data input ce=h vref av dd =dv dd =4.75 to 5.25 v ta= 20 to +75 c av dd =dv dd =4.75 to 5.25 v ta= 20 to +75 c r out =75 ? r out =75 ? ce=h l ce=l h min. 0.5 2.5 0.3 1.8 0 1 2.4 5 5 10 typ. 8 2.0 1.5 10 30 57 10 2 2 max. 40 2.5 0.3 2.2 3.0 15 1 32 1.2 9 0.8 5 4 4 unit bit msps lsb lsb v % ma mv pv s db ma m ? pf v a ns ns ns ms ms
6 CXD1177Q yck 8bit counter with latch clk 40mh z square wave cck 0.1 dvss 200 avss avss blk ce vb yo co y0 to y7 1 to 8 c0 to c7 9 to 16 vg vref iref 1k avss 17 18 19 20 22 24 25 27 29 30 0.1 3.3k 200 av dd oscilloscope crosstalk measurement circuit yck digital waveform generator clk 40mh z square wave cck 0.1 dvss 200 avss avss blk ce vb yo co y0 to y7 1 to 8 c0 to c7 9 to 16 vg vref iref 1k avss 17 18 19 20 22 24 25 27 29 30 0.1 3.3k 200 av dd all 1 spectrum analyzer setup time hold time measurement circuit glitch energy yck clk 1mh z square wave cck 0.1 dvss 75 avss avss blk ce vb yo co y0 to y7 1 to 8 c0 to c7 9 to 16 vg vref iref 1k avss 17 18 19 20 22 24 25 27 29 30 0.1 1.2k 75 av dd delay controller 8bit counter with latch delay controller oscilloscope } maximum conversion velocity measurement circuit
7 CXD1177Q dc characteristics measurement circuit yck clk 40mh z square wave cck 0.1 dvss 200 avss avss blk ce vb yo co y0 to y7 1 to 8 c0 to c7 9 to 16 vg vref iref 1k avss 17 18 19 20 22 24 25 27 29 30 3.3k 200 av dd controller 0.1 dvm yck frequency demultiplier clk 10mh z square wave cck 0.1 dvss 200 avss avss blk ce vb yo co y0 to y7 1 to 8 c0 to c7 9 to 16 vg vref iref 1k avss 17 18 19 20 22 24 25 27 29 30 0.1 3.3k 200 av dd oscilloscope propagation delay time measurement circuit
8 CXD1177Q t pw1 t pw0 aaa aaa aa aa aa aa aa aa t s t h t s t h t s t h t pd t pd t pd clk data d/a out 100% 50% 0% 2v i/o chart (when full-scale output voltage at 2.00 v) input code output voltage msb lsb 1 1 1 1 1 1 1 1 : 1 0 0 0 0 0 0 0 : 0 0 0 0 0 0 0 0 2.0 v 1.0 v 0 v description of operation timing chart y out c out 200 avss 200 avss avss avss av dd 1k 3.3k avss dvss 0.1f dvss (msb) (lsb) (msb) (lsb) dv dd av dd 0.1f 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 2 3 4 5 6 7 8 1 c in clock y in application circuit application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility fo r any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same . note) even though only 1 channel is used, be sure to input the clock signal to yck(pin 19).
9 CXD1177Q notes on operation how to select the output resistance the CXD1177Q is a d/a converter of the current output type. to obtain the output voltage connect the resistance to the current output pins y0, c0. for specifications we have; output full scale voltage v fs = 1.8 to 2.2 [v] output full scale current i fs = less than 15 [ma] calculate the output resistance value from the relation of v fs = i fs r out . also, 16 times resistance of the output resistance is connected to reference current pin i ref . in some cases, however, this turns out to be a value that does not actually exist. in such a case a value close to it can be used as a substitute. here please note that v fs becomes v fs = v ref 16r out /r ir . r out is the resistance connected to the current output pins yo and co while r ir is connected to i ref . increasing the resistance value can curb power consumption. on the other hand glitch energy and data settling time will inversely increase. set the most suitable value according to the desired application. phase relation between data and clock to obtain the expected performance as a d/a converter, it is necessary to set properly the phase relation between data and clock applied from the exterior. be sure to satisfy the provisions of the setup time (t s ) and hold time (t h ) as stipulated in the electrical characteristics. power supply and grand to reduce noise effects separate analog and digital systems in the device periphery. for the power supply pins, both digital and analog, bypass respective grounds by using a ceramic capacitor of about 0.1 f, as close as possible to the pin. latch up av dd and dv dd have to be common at the pcb power supply source. this is to prevent latch up due to voltage difference between av dd and dv dd pins when power supply is turned on. yo and io pins the yo and io pins are the inverted current output pins described in the pin description. the sums shown below become the constant value for any input data. a) the sum of the currents output form yo and yo b) the sum of the currents output form co and co however, the performances such as the linearity error of the inverted current output pin output current is not guaranteed. clock input signal even though only 1 channel is used, be sure to input the clock signal to yck(pin 19).
10 CXD1177Q c av ss dv ss av ss dv ss av dd dv dd CXD1177Q dv dd digital ic 31 21 23 32 c +5v latch up prevention the CXD1177Q is a cmos ic which requires latch up precautions. latch up is mainly generated by the lag in the voltage rising time of av dd (pin 31) and dv dd (pin 32), when power supply is on. 1. correct usage a. when analog and digital supplies are from different sources b. when analog and digital supplies are from a common source (i) (ii) av dd +5v av ss dv ss av ss dv ss av dd dv dd CXD1177Q dv dd digital ic 31 21 23 32 c c +5v av ss dv ss av ss dv ss av dd dv dd CXD1177Q dv dd digital ic 31 21 23 32 c c +5v
11 CXD1177Q 2. example when latch up easily occurs a. when analog and digital supplies are from different sources b. when analog and digital supplies are from common source (i) (ii) av dd +5v av ss dv ss av ss dv ss av dd dv dd CXD1177Q dv dd digital ic 21 23 32 c 31 +5v c av ss dv ss av ss dv ss av dd dv dd CXD1177Q dv dd digital ic av dd 31 21 23 32 +5v +5v av ss dv ss av ss dv ss av dd dv dd CXD1177Q dv dd digital ic av dd 31 21 23 32
12 CXD1177Q example of representative characteristics 1.0 0 1.0 2.0 reference voltage vs. output full scale voltage reference voltage v ref [v] output full scale voltage v fs [v] 2.0 0255075 25 0 output full scale voltage v fs [v] 1.9 2.0 ambient temperature vs. output full scale voltage ambient temperature ta [ c] 100 100 output resistance vs. glitch energy output resistance r out [ ? ] glitch energy ge [pv s] 200 200 100k 1m crosstalk ct [db] 50 60 output frequency vs. crosstalk output frequency f o [hz] 10m 40 av dd =dv dd =5.0v r out =200 ? r ir =3.3k ? ta=25 c av dd =dv dd =5.0v v ref =2.0v r ir 16r out ta=25 c av dd =dv dd = 5.0v v ref =2.0v r out =200 ? r ir =3.3k ? av dd =dv dd = 5.0v v ref =2.0v r out =200 r ir =3.3k ta=25 c ? ?
sony code eiaj code jedec code package material lead treatment lead material package mass epoxy resin solder plating 42 alloy 32pin qfp (plastic) 9.0 0.2 7.0 0.1 1.5 0.15 (8.0) 0.1 0.1 + 0.2 + 0.35 + 0.3 0.50 0.127 0.05 + 0.1 0 to 10 0.8 0.3 0.1 + 0.15 1 8 9 32 16 17 24 25 m 0.24 0.2g qfp-32p-l01 qfp032-p-0707 0.1 package outline unit : mm CXD1177Q 13 sony corporation

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